The packaging density in electronic industry continuously increases to accommodate more electronic devices into a package. Three-dimensional (“3D”) wafer-to-wafer stacking technology substantially contributes to the device integration process. Typically, a wafer has layers of integrated circuitry, e.g., processors, programmable devices, memory devices, and the like, built on a silicon substrate. A top layer of the wafer may be connected to a bottom layer of the wafer through silicon interconnects (“vias”). To form a 3D wafer stack, two or more wafers are placed on top of each other and bonded. 3D wafer stacking technology offers a number of potential benefits, including improved form factors, lower costs, enhanced performance, and greater integration through system-on-chip (“SOC”) solutions. The 3D wafer stacking technology may provide additional functionality to the chip. After being formed, the 3D wafer stack may be diced into stacked dies (“chips”), each stacked chip having multiple tiers (“layers”) of integrated circuitry. SOC architectures formed by 3D wafer stacking can enable high bandwidth connectivity of products, e.g., logic circuitry and dynamic random access memory (“DRAM”), that otherwise have incompatible process flows. There are many applications for 3D wafer stacking technology, including high performance processing devices, video and graphics processors, high density and high bandwidth memory chips, and other SOC solutions.
FIG. 1 shows a cross-sectional view of a typical 3D wafer stack 100 having backside connections. As shown in FIG. 1, wafer 110 has a device region 102 built upon a front side of substrate 101, and wafer 120 has a device region 105 built upon a front side of substrate 106. Typically, each of substrate 101 and substrate 106 is a silicon substrate. Each of device region 102 and device region 105 includes integrated circuitries with active and passive devices. Wafer 110 is bonded to wafer 120 through conductive pads 103 and 104 located in respective device regions 102 and 105, as shown in FIG. 1. As shown in FIG. 1, 3D wafer stack has a dielectric layer 108 on a back side of substrate 106. Backside vias 111 filled with copper extend through the dielectric layer 108 to conductors 107 in device region 106, as shown in FIG. 1. Insulating layer 109 is formed on sidewalls of vias 111, as shown in FIG. 1. Conductive bumps 112 are placed directly on top of vias 111 to form backside connections 113, as shown in FIG. 1.
As shown in FIG. 1, 3D wafer stacked architecture integrates more electronic devices comparing with a conventional planar architecture, such that more electrical power is needed to be supplied through backside connections 113 to device regions 105 and 103. Backside connections 113, however, may deliver to device regions 105 and 103 only limited amount of the electrical power through conductive bumps 112 and vias 111 without being damaged. Backside connections 113 that consist of conductive bumps 112 placed directly vertically on top of vias 111 that are formed in the dielectric layer 108 cause direct vertical stress transfer into dielectric layer 108 and to an interface between 3D wafer stack 100 and a package (not shown). The direct vertical stress deteriorates thermal and mechanical stability of the 3D wafer stack 100. The limited power delivery and stress transfer not only negatively impact the operation, but also cause significant reliability problems for 3D wafer stack 100. Further, present manufacturing flow for backside connections for 3D wafer stack 100 is very complicated and expensive, and involves many additional operations, e.g., to provide additional re-routing capabilities, and to increase the amount of power delivered to electronic devices.